Intel’s Core Ultra 400 Nova Lake Leak Reveals Massive 150mm² CPU Tile to Battle AMD’s 3D V-Cache

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Intel Goes Big on Cache: Nova Lake’s “bLLC” Tile Could Be 36% Larger to Rival AMD 3D V-Cache

The desktop CPU wars are heating up once again. Fresh leaks surrounding Intel’s upcoming Core Ultra 400 series, codenamed Nova Lake-S, suggest the company is preparing a serious response to AMD’s wildly popular 3D V-Cache technology. According to details shared by hardware leaker HXL, Intel is developing a “Big Last Level Cache” (bLLC) strategy that takes a very different engineering approach—one that comes with a significant increase in physical die size.

Intel’s Core Ultra 400 Nova Lake Leak Reveals Massive 150mm² CPU Tile to Battle AMD’s 3D V-Cache
Intel’s Core Ultra 400 Nova Lake Leak Reveals Massive 150mm² CPU Tile to Battle AMD’s 3D V-Cache

Unlike AMD’s method of stacking extra cache vertically on top of the compute chip (3D V-Cache), Intel is rumored to be integrating this massive pool of cache directly into the silicon of the CPU tile itself. While this avoids the complexity of stacking dies, it does come with a trade-off: space.

A 36% Larger Compute Tile

The leaker claims that a standard Nova Lake compute tile without the bLLC enhancement would measure approximately 110mm². The version featuring the integrated Big Last Level Cache, however, would balloon to 150mm². That is a 36% increase in footprint for a single tile.

This is not just a minor revision; it is a significant re-engineering of the physical processor. For context, adding 40mm² of silicon purely for cache is an expensive and space-intensive strategy, but it suggests Intel is betting big on cache-sensitive workloads—namely, gaming.

Up to 288MB of Cache and 52 Cores

If the rumors hold, the cache numbers will be equally impressive. The bLLC is reportedly sized at 144MB per compute tile. This means a high-end dual-tile configuration, rumored for a potential Core Ultra 9 SKU, could feature a staggering 288MB of total cache.

This would put Intel directly in competition with AMD’s next-generation Ryzen 10000X3D series, which is rumored to increase its 3D V-Cache capacity from 64MB to 96MB per CCD, yielding 192MB in dual-CCD configurations. Intel would hold a mathematical advantage in raw cache volume, though real-world performance will ultimately depend on latency and architecture efficiency.

The leaker also outlined potential SKU configurations:

  • Core Ultra 9: 52 cores (dual compute tile design) with 288MB bLLC
  • Core Ultra 7: 28 cores (single tile) with 144MB bLLC

These configurations include a mix of Performance-cores (P-cores), Efficient-cores (E-cores), and Low Power E-cores (LPE), showcasing a highly complex heterogeneous architecture.

Why This Matters

AMD’s Ryzen 9000X3D processors are currently dominating sales charts and have become the gold standard for high-end PC gaming. The extra cache effectively reduces CPU bottlenecks, allowing processors to perform well even with standard DDR5 memory kits. Intel has lacked a direct competitor to this proposition—until now.

By embedding the cache directly into the tile, Intel may be aiming for lower latency than AMD’s stacked solution, though yields and thermal density will be challenges given the enlarged die.

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The Road Ahead

It is important to note that Intel has not officially confirmed Nova Lake specifications, let alone the bLLC feature. These leaks are likely emerging as Intel begins sharing early roadmaps with partners ahead of a projected launch. Meanwhile, AMD is not standing still. The company is reportedly preparing Zen 6-based Ryzen 10000 series processors, which will move from 8-core to 12-core CCDs while increasing their 3D V-Cache capacity.

If these rumors prove accurate, 2026 and 2027 could mark the most competitive era for desktop processors in a decade—with both teams bringing heavy artillery in the form of massive on-chip cache.

Source: HXL

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